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[personal profile] izard
Yesterday Akhilesh Kumar, the Skylake-SP CPU architect announced mesh architecture for future Xeon CPU,

that replaces ring. The ring was there in Xeon for 6 generations, and once the server CPU has grown from 4 to 20+ cores, latency of the ring became an important factor to consider in software performance work. In last 4 architectures, there were even sub-rings (Cluster-on-Die) to address this. Some folks were reverse-engineering a secret (though simple) hash function that directed different cache lines to different chunks of last level cache.

No need any more. That is just one of great features in the upcoming CPU.
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